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| May 1999 PRELIMINARY ML4804 Power Factor Correction and PWM Controller Combo GENERAL DESCRIPTION The ML4804 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specification. Intended as a BiCMOS enhancement of the industry-standard ML4824, the ML4804 includes circuits for the implementation of leading edge, average current, "boost" type power factor correction and a trailing edge, pulse width modulator (PWM). It also includes a TriFault DetectTM function to help ensure that no unsafe conditions will result from single component failure in the PFC. 1A gate-drive outputs minimize the need for external driver circuits. Low power requirements improve efficiency and reduce component costs. An over voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. FEATURES s Internally synchronized leading-edge modulated PFC and trailing-edge modulated PWM in one IC TriFault DetectTM for UL1950 compliance and enhanced safety VCCOVP provides additonal PFC fault protection Slew rate enhanced transconductance error amplifier for ultra-fast PFC response Low power: 200A startup current, 5.5mA operating current Low total harmonic distortion, high PF Reduces ripple current in the storage capacitor between the PFC and PWM sections Average current, continuous boost leading edge PFC PWM configurable for current-mode or voltage mode operation Overvoltage and brown-out protection, UVLO, and soft start s s s s s s s s s BLOCK DIAGRAM 16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 RAMP 2 8 OSCILLATOR DUTY CYCLE LIMIT + + - 1 IEAO POWER FACTOR CORRECTOR TRI-FAULT + - 13 OVP + 2.75V VCCOVP VCC 16.4V + + - - VCC 17V VCC 7.5V REFERENCE Q Q PFC OUT Q Q 12 VREF 14 VEA 1.6k + IEA 0.5V S -1V + - GAIN MODULATOR 1.6k R S R - PFC ILIMIT VDC 6 VCC SS 5 25A 1.25V S VFB 2.45V + Q Q PWM OUT 11 VIN OK 1.0V + + R DC ILIMIT DC ILIMIT 9 VREF PULSE WIDTH MODULATOR VCC UVLO 1 ML4804 PIN CONFIGURATION ML4804 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) IEAO 1 IAC 2 ISENSE 3 VRMS 4 SS 5 VDC 6 RAMP 1 7 RAMP 2 8 16 VEAO 15 VFB 14 VREF 13 VCC 12 PFC OUT 11 PWM OUT 10 GND 9 DC ILIMIT TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 2 3 4 5 6 7 8 IEAO IAC I SENSE V RMS SS VDC RAMP 1 RAMP 2 Slew rate enhanced PFC transconductance error amplifier output PFC AC line reference input to Gain Modulator Current sense input to the PFC Gain Modulator PFC Gain Modulator RMS line voltage compensation input Connection point for the PWM soft start capacitor 9 10 11 12 13 14 15 DC ILIMIT GND PWM OUT PFC OUT VCC V REF V FB VEAO PWM cycle-by-cycle current limit comparator input Ground PWM driver output PFC driver output Positive supply Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output PWM voltage feedback input Oscillator timing node; timing set by RTCT When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM modulation ramp input. 16 2 ML4804 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC ............................................................................................... 18V ISENSE Voltage ............................................... -5V to 0.7V Voltage on Any Other Pin .... GND - 0.3V to VCCZ + 0.3V I REF ............................................................................................ 10mA IAC Input Current .................................................... 10mA Peak PFC OUT Current, Source or Sink ....................... 1A Peak PWM OUT Current, Source or Sink ..................... 1A PFC OUT, PWM OUT Energy Per Cycle .................. 1.5J Junction Temperature .............................................. 150C Storage Temperature Range ...................... -65C to 150C Lead Temperature (Soldering, 10 sec) ..................... 260C Thermal Resistance (JA) Plastic DIP .......................................................... 80C/W Plastic SOIC ...................................................... 105C/W OPERATING CONDITIONS Temperature Range ML4804CX .................................................... 0C to 70C ML4804IX .................................................. -40C to 85C ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 15V, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE ERROR AMPLIFIER Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio OVP COMPARATOR Threshold Voltage Hysteresis 2.65 2.75 250 2.85 325 V mV 11V < VCC < 16.5V VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V -40 40 60 60 6.0 VNON INV = VINV, VEAO = 3.75V -1.5 50 0 100 4 -0.5 6.7 0.65 -104 160 70 75 1.0 2 150 15 -1.0 V 11V < VCC < 16.5V VIN = 2.5V 0.5V, VOUT = 6V VIN = 2.5V 0.5V , VOUT = 1.5V -40 40 50 50 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V 0 30 2.43 65 2.5 -0.5 6.7 0.1 -140 140 60 60 0.4 5 90 2.57 -1.0 V V A V V A A dB dB mV A V V A A dB dB 3 ML4804 ELECTRICAL CHARACTERISTICS SYMBOL TRI-FAULT DETECT Fault Detect HIGH Time to Fault Detect HIGH Fault Detect LOW VCCOVP COMPARATOR Threshold Voltage Hysteresis PFC ILIMIT COMPARATOR Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output DC ILIMIT COMPARATOR Threshold Voltage Input Bias Current Delay to Output VIN OK COMPARATOR Threshold Voltage Hysteresis GAIN MODULATOR Gain (Note 3) IAC = 100A, VRMS = VFB = 0V IAC = 50A, VRMS = 1.2V, VFB = 0V IAC = 50A, VRMS = 1.8V, VFB = 0V IAC = 100A, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage PFC Dead Time CT Discharge Current VRAMP 2 = 0V, VRAMP 1 = 2.5V 170 3.5 Line, Temp 68 2.5 250 5.5 330 7.5 TA = 25C 11V < VCC < 16.5V 71 76 1 2 84 81 kHz % % kHz V ns mA IAC = 100A IAC = 350A, VRMS = 1V, VFB = 0V 0.60 0.60 1.8 0.85 0.20 0.80 2.0 1.0 0.30 10 0.75 0.9 1.05 2.40 1.25 0.40 MHz V 2.35 0.8 2.45 1.0 2.55 1.2 V V 0.95 1.0 0.3 150 1.05 1 300 V A ns -0.9 120 -1.0 220 150 300 -1.1 V mV ns TA = Operation Temp Range TA = Operation Temp Range 1.7 16.4 2.0 2.3 V V VFB = VFAULT DETECT LOW to VFB =OPEN; 470pF from VFB to GND 0.4 2.65 2.75 2 0.5 2.85 4 0.6 V ms V PARAMETER CONDITIONS MIN TYP MAX UNITS 4 ML4804 ELECTRICAL CHARACTERISTICS SYMBOL REFERENCE Output Voltage Line Regulation Load Regulation TA = 25C, I(VREF) = 1mA 11V < VCC < 16.5V 0mA < I(VREF) < 10mA; TA = 0C to 70C 0mA Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. Note 3: Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x [IAC (VEAO - 0.625)]-1; VEAOMAX=5V. Note 4: UVLO Hysteresis 5 ML4804 TYPICAL PERFORMANCE CHARACTERISTICS 180 160 TRANSCONDUCTANCE ( ) 140 120 100 80 60 40 20 0 0 1 2 VFB (V) 3 4 5 Voltage Error Amplifier (VEA) Transconductance (gm) 180 VARIABLE GAIN BLOCK CONSTANT (K) 540 480 420 300 240 180 120 60 0 160 TRANSCONDUCTANCE ( ) 140 120 100 80 60 40 20 0 -500 Current Error Amplifier (IEA) Transconductance (gm) K= 0 IEA INPUT VOLTAGE (mV) 500 0 1 2 VRMS(V) 3 4 5 Gain Modulator Transfer Characteristic (K) IAC x 5V 0.625V bI GAINMOD a 84A g f 6 ML4804 FUNCTIONAL DESCRIPTION The ML4804 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM's line regulation. In either mode, the PWM stage uses conventional trailingedge duty cycle modulation, while the PFC uses leadingedge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4804 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features have been built into the ML4804. These include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. POWER FACTOR CORRECTION PFC SECTION Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peakcharging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in-phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4804 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. One of these conditions is that the Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4804. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1) A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2) A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator's output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Typical Performance Characteristics. 3) The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. In order to prevent ripple, which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4804 PFC is of the current-averaging type, no slope compensation is required. 7 ML4804 FUNCTIONAL DESCRIPTION (Continued) boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. TriFault DetectTM Current Error Amplifier The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the 16 VEAO IEAO OVP + The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: IGAINMOD = IAC x VEAO x 1V VRMS 2 (1) More exactly, the output current of the gain modulator is given by: IGAINMOD = K x (VEAO - 0.625V ) x IAC where K is in units of V-1. Note that the output current of the gain modulator is limited to 500A. To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards, the ML4800 (ML4804) includes TriFault Detect. This feature monitors VFB (Pin 15) for certain PFC fault conditions. In the case of a feedback path failure, the output of the PFC could go out of safe operating limits. With such a failure, VFB will go outside of its normal operating area. Should VFB go too low, too high, or open, TriFault Detect senses the error and terminates the PFC output drive. TriFault detect is an entirely internal circuit. It requires no external components to serve its protective function. 1 TRI-FAULT 0.5V + - 2.75V - VCCOVP VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 OSCILLATOR R Q GAIN MODULATOR 1.6k VEA - + - - VCC 1.6k + + + - IEA 16.4V S -1V + - Q Q PFC OUT Q 12 R S PFC ILIMIT Figure 1. PFC Section Block Diagram 8 ML4804 FUNCTIONAL DESCRIPTION Overvoltage Protection The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.75V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.50V. The VFB should be set at a level where the active and passive external power components and the ML4804 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. VCCOVP The VCCOVP feature of the ML4804 works along with the TriFaultTM Detect as a redundant PFC buss voltage limiter, to prevent a damaged and broken connection or component from causing an unsafe fault condition. VCCOVP assumes that VCC is generated from a bootstrap winding on the PFC boost inductor, or by some other means whereby VCC is proportional to VBUSS. If the proportionality is exact, then a nominal VBUSS of 385V at VCC = 15.0V will cause the VCCOVP comparator to shut the PFC down when VBUSS = [(16.4/15.0) x 385V] = 444V. The PFC will then remain in the shutdown state until VCC declines to 13.0V, at which time the PFC will restart. If the PFC VCC again encounters an over voltage condition, the protection cycle will repeat. Note that the PWM stage of the ML4804 remains operational even when the PFC goes into VCCOVP shutdown. For a real-world example, assume that the bootstrap supply is derived from a conventional boost inductor winding and rectified using Shottky diodes. Then it follows VREF (Continued) that the voltage from the bootstrap winding must equal 15.8V during regular circuit operation, and will increase to 17.2V at the point of VCCOVP shutdown. Then the output voltage from the PFC will have increased from a noninal VBUSS of 385VDC to (17.2/15.8) x 385V = 419VDC. When VBUSS reaches 419V, the PFC will shut off, thereby protecting the output (BUSS) capacitor and the semiconductors in both the PFC and PWM stages. To assure reasonable headroom in which to operate this device, VCCOVP tracks with UVLO. The VCCOVP threshold is always at least 2V above that of the UVLO. To assure reliable operation of the ML4804, VCC must be operated from a bootstrap winding on the PFC's inductor, or from an external power supply whose output is regulated to 15.0V (nominal). In the case of a regulated power supply powering the ML4804, the VCCOVP function will be rendered non-operational. Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the PFC's two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the PFC OUTPUT VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 VEA - VBIAS 16 IEAO 1 RBIAS IEA + VCC + - + - ML4804 GND 0.22F CERAMIC 15V ZENER GAIN MODULATOR Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers Figure 3. External Component Connections to VCC 9 ML4804 FUNCTIONAL DESCRIPTION (Continued) at VREF = 7.5V: t RAMP = C T x R T x 0.51 voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier's open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the ML4804's voltage error amplifier has a specially shaped nonlinearity such that under steadystate operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the design of this class of PFC. Oscillator (RAMP 1) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: fOSC = 1 t RAMP + t DEADTIME The deadtime of the oscillator may be determined using: t DEADTIME = 2.5V x C T = 450 x C T 55mA . (4) The deadtime is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: fOSC = 1 t RAMP (5) EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: fOSC = 100kHz = 1 t RAMP Solving for RT x CT yields 1.96 x 10-4. Selecting standard components values, CT = 390pF, and RT = 51.1k. The deadtime of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator deadtime, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT. PWM SECTION Pulse Width Modulator The PWM section of the ML4804 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter's output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP 2 in such applications. For voltagemode operation or certain specialized applications, RAMP 2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input would is used for output stage overcurrent protection. (2) The deadtime of the oscillator is derived from the following equation: t RAMP = C T x R T x In FG V HV REF REF - 125 . - 3.75 IJ K (3) 10 ML4804 FUNCTIONAL DESCRIPTION (Continued) feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25A supplies the charging current for the capacitor, and startup of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: C SS = t DELAY x 25A . 125V No voltage error amplifier is included in the PWM stage of the ML4804, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM's RAMP 2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V. PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.45V. Once this voltage reaches 2.45V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. PWM Control (RAMP 2) When the PWM section is used in current mode, RAMP 2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM's output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), that will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, (6) where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS: C SS = 5ms x 25A = 100nF 125V . (6a) Generating VCC The ML4804 is a voltage-fed part. It requires an external 15V, 10% (or better) shunt voltage regulator, or some other VCC regulator, to regulate the voltage supplied to the part at 15V nominal. This allows low power dissipation while at the same time delivering 13V nominal gate drive at the PWM OUT and PFC OUT outputs. If using a Zener L1 + I1 VIN SW2 I2 I3 I4 DC SW1 C1 RL RAMP VEAO REF U3 + -EA DFF RAMP OSC U4 CLK + - U1 R Q D U2 Q CLK VSW1 TIME TIME Figure 4. Typical Trailing Edge Control Scheme 11 ML4804 FUNCTIONAL DESCRIPTION (Continued) turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 5 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary "no-load" period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC's output ripple voltage can be reduced by as much as 30% using this method. diode for this function, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor's value must be chosen to meet the operating current requirement of the ML4804 itself (8.5mA, max.) plus the current required by the two gate driver outputs. EXAMPLE: With a VBIAS of 20V, a VCC of 15V and the ML4804 driving a total gate charge of 90nC at 100kHz (e.g., 1 IRF840 MOSFET and 2 IRF820 MOSFETs), the gate driver current required is: IGATEDRIVE = 100kHz x 90nC = 9mA RBIAS = RBIAS = VBIAS - VCC ICC + IG + Iz 20V - 15V = 250 6mA + 9mA + 5mAIz (7) (8) Choose RBIAS < 240 The ML4804 should be locally bypassed with a 1.0F ceramic capacitor. In most applications, an electrolytic capacitor of between 47F and 220F is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. TYPICAL APPLICATIONS Figure 6 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33. LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will L1 + I1 VIN SW2 I2 I3 I4 DC SW1 C1 RL RAMP VEAO U3 + -EA REF VEAO + - CMP U1 DFF R Q D U2 Q CLK VSW1 TIME RAMP OSC U4 CLK TIME Figure 5. Typical Leading Edge Control Scheme 12 F1 3.15A BR1 4A, 600V KBL06 Q1G C4 4.7nF C5 100F R19 33 Q2 C25 0.1F R24 10k D5 600V D7 16V T2 D11A L2 L3 T1B R13 383k Q1 R20 22 IN5820 R14 383k L1B Q3G D11B Q3 C20 0.47F R17 3 R21 2.2 R22 2.2 R30 1.5k C22 10F R32 8.66k T1A C7 150pF R37 1k Q4 D4 5.1V ML4804 1 IEAO IAC ISENSE VRMS SS VDC RTCT RAMP 1 RAMP 2 9 GND 10 D8 PWM OUT 11 C31 330pF R15 4.99k D10 C15 1.0F C13 0.22F C8 150nF C9 15nF PFC OUT 12 J8 C10 10F VCC 13 VREF 14 U1 VFB 15 VFB VDC 16 VCC REF R40 470 R11 412k R26 10k 2 3 4 5 6 7 8 R25 10k U2 R44 10k R12 68.1k C6 1.5nF R23 220 PWM ILIMIT D6 600V C24 0.47F D2 0.22F C26 D3 0.22F D12 16V IN5820 R10 249k R18 33 C21 1500F C32 0.47F C30 1000F Q2G R27 82k R1 357k R9 249k R2 357k L1A VBUSS D1 8A HFA08TB60 AC INPUT 85 TO 260V C1 0.47F ISENSE 12V 12V, 100W R5 1.2 R6 1.2 R7 1.2 R8 1.2 C3 R3 0.22F 100k R38 51.1k R16 10k R4 13.2k R29 1.2k R34 240 C2 0.47F R39 33 RT/CT R31 10k D14 1N914 C19 0.22F C18 390pF C23 10nF VDC U3 TL431C D13 1N914 C11 220pF D15 1N914 C28 220pF R33 2.26k PRI GND 12V RET 12V RETURN Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33 NOTE: D8, D10; IN5818 D3, D5, D6, D12; BYV26C D11; MBR2545CT L1; 3MHz L2; PREMIER MAGNETICS VTP-05007 L3; PREMIER MAGNETICS TSD-904 T1; PREMIER MAGNETICS PMGD-03 T2; PREMIER MAGNETICS TSD-735 UNUSED DESIGNATORS; C14, C16, C17, C27, C29, C33, D9, R36, R35, R42, R43, ML4804 13 ML4804 ORDERING INFORMATION PART NUMBER ML4804CP ML4804CS ML4804IP ML4804IS TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C -40C to 85C PACKAGE 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) (c) Micro Linear 1999. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com DS4804-01 14 |
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